1. Technical Field
This invention relates in general to improved interfaces between pin connectors and printed circuit boards, and in particular to improved printed circuit boards. Still more particularly, the invention relates to an improved tab design for printed circuit board connector edges.
2. Description of the Prior Art
As the designs of computer processors and other supporting hardware become increasing complex, so too are the physical designs of the printed circuit boards, such as mother boards and daughter boards, that they utilize. For example, in circuit boards that contain advanced, high-speed, impedance-controlled channels, it is difficult to match impedances at the connector interfaces. Generally, impedance has two aspects: resistance and reactance. Resistance impedes current by converting electrical energy to heat and is always greater than zero. Reactance impedes current, but varies with frequency and can be positive or negative. The electrical characteristics of the connectors and the associated via patterns on circuit boards tend to present highly inductive influences on the signal lines. These inductive influences create discontinuities in the line impedance which, in turn, cause reflection noise on the signal lines, thereby degrading the overall quality of the signals.
Although the size of the edge tabs on daughter cards can be increased to compensate for the effects of the impedance discontinuities, there are several mechanical factors which limit the extent to which the size of the edge tabs may be increased. As shown in FIG. 1, the first limitation is the mechanical requirement that "vertical" (top to bottom) plated pathways 11 be provided for the mother board connector pins (not shown) which mate to the "upper" row 13 of contacts 15. The plated pathways 11 allow the connector pins to slide from the beveled perimeter edge 17 of the daughter card 19 up to the contact areas on the upper edge tabs (indicated schematically at 21) without grinding on the bare fiberglass substrate 23 of the daughter card 19. Such grinding would lead to premature wear of the connector pins which, in turn, would cause intermittent electrical contacts and short circuits between the signal wires passing through the connector.
The "lower" row 25 of contacts 27 are touched by the connector pins at areas 29. The lower row contacts 27 are typically used for signal line connections and have a size limitation in the "horizontal" direction (left to right in FIG. 1). The lower edge contacts 27 require a safety buffer 31 of about 5 mils from the plated pathways 11 between each signal contact 27. Violating this minimum distance for buffer gaps can cause short circuits between the pathways, thereby shorting the upper row of reference contacts 15.
The second limiting factor is the electrical effect of the capacitive pad area on the actual connector pin contact area. Increasing the signal pad area upward, or in the vertical direction, has diminishing returns. The farther away the capacitive area is from the pin contact area, the less effect it will offer in compensating for the impedance mismatch at the connector interface. Thus, an improved printed circuit board card edge design which overcomes the limitations of the prior art is needed. It would be desirable to provide an improved printed circuit board card edge design which has sufficient contact area without resulting in inductive effects.